1. Field of the Invention
The present invention relates to a display screen having an optical mask and to a process for producing said screen.
It is used in the production of display screens intended to operate under severe conditions, i.e. intense lighting and high temperatures. The screen according to the invention can be used for television sets, computers, vehicle dashboards and instrument panels (cars, aircraft,etc.).
2. Description of the Prior Art
A display screen essentially comprises two transparent plates holding between them an electro-optical material and in particular a liquid crystal. FIGS. 1 and 2 show constructional examples of such plates.
FIG. 1 shows a transparent, e.g. glass substrate 10 covered by a group of conducting addressing columns 12, e.g. of indium and tin oxide (ITO), an array of electrodes 14, each of which constitutes a display point or pixels and a group of addressing rows 16 generally constituted by a stack of layers, namely a semiconductor layer (e.g. of aSi:H), an insulating layer (e.g. of SiN) and a conducting layer (e.g. of aluminium).
The columns 12 are extended by a crook 18 and the electrodes 14 by a finger 20, so that these various appendages and the column form the source and the drain of a double thin film transistor (TFT), the two gates being constituted by the metal layer of the addressing row.
FIG. 2 shows a second plate with a second transparent substrate 30 (e.g. of glass), blocks 32 of coloured filters (red, green, blue) a black matrix 34 and a conductive, transparent counterelectrode 36. The coloured filters 32 and the black matrix 34 are not essential in the invention to be described hereinafter, but would still be useful.
A screen of this type, or at least the first plate illustrated in FIG. 1, can be produced by a process only requiring two photolithography levels, as described in FR-A-2 533 072.
To ensure that an excessively intense illumination does not disturb the operation of the transistors, it is known to place an optical mask beneath each of them. Such a solution is e.g. described by the article of TOMISHISA SUNATA et al entitled "A Large-Area High-Resolution Active-Matrix Color LCD Addressed by a-Si TFT's", published in the journal "Proceedings of the Society for Information Display (SID)", 27, 1986, no.3, pp.229-233.
However, this mask, which is generally constituted by an opaque metal layer, has the effect of creating a parasitic transistor below the transistor to be protected. If the mask is at a floating potential, it can rise by influence to a positive potential and lead to leakage currents, which are prejudicial to the operation of the screen.
Consideration has been given to connecting such a mask to one of the transistor electrodes in order to fix the potential thereof. This is what is e.g. proposed in EP-A-179 915. The structure used is shown in FIG. 3. On a glass substrate 40 there is a mask 42 connected to an addressing column 43, everything being covered by an insulator 44. On said insulator 44 there is metal electrode 46 defining the pixel, said electrode being extended by a segment 47 serving as a drain. Moreover, there is a semiconductor 48 and a metal layer 50 serving as the source. An opening 82 is made in the insulator 44 for connecting the mask 42 to the source 50. The transistor is completed by an insulating layer 54 and by a metal gate or grid 56.
However, this device suffers from a disadvantage. Thus, liquid crystal screens are always excited in alternating manner. Thus, what serves as the transistor source in one frame serves as its drain in the other. Therefore the transistors of a screen of the type described hereinbefore will necessarily function with a zero gate--drain voltage in one of the frames. The current--voltage characteristic will then be of the diode type and if the voltage between the source and the drain exceeds a threshold voltage, the current will become very high.
FIGS. 4 and 5 provide a better understanding of this disadvantage of the prior art. FIG. 4 shows an electric diagram with a main transistor T1 and a parasitic transistor T2 created by the optical mask 42. The points A and B mark the zones corresponding alternately to the source and the drain of the transistor, as a function of the frame displayed.
Part a of FIG. 5 shows the source--drain current characteristic (I.sub.SD) as a function of the source--drain voltage (V.sub.SD) for a zero gate--source voltage (V.sub.GS) and namely for the parasitic transistor T2 during one frame. In part b of FIG. 5 it is possible to see the same characteristic for a zero gate--drain voltage V.sub.GD, which takes place for the following frame. This part b consequently shows that the source--drain current I.sub.SD can become very high.
Thus, in summarizing, for a negative frame the voltage V.sub.o applied to the addressing column is negative. If the voltage at A is below the voltage at B, A constitutes the source of the transistor T1 and the parasitic transistor T2 functions with a zero gate --source voltage (V.sub.GS), whereas the source--drain current I.sub.SD is low, no matter what the source--drain voltage (V.sub.SD) (part a of FIG. 5). For a positive frame the voltage V.sub.o is positive. If the voltage at A exceeds the voltage at B, point A corresponds to the drain. The parasitic transistor T2 functions at VGD=0. The current I.sub.SD can be high if V.sub.SD exceeds a threshold (part b of FIG. 5).
Therefore the prior art solution leads to the disadvantage of causing a leakage current in one of the two frames.
EP-A-136 509 proposes another solution, which consists of introducing below the thin film transistors an optical mask, which can partly pass beneath the pixel. The leakage current in the transistor is reduced and a supplementary storage capacity is formed.
This document stipulates that the optical mask must be located below the columns of the matrix (as well as below the TFT's and partly below the pixels). In this configuration, the time constant of the columns becomes non-negligible compared with the addressing time, which leads to a distortion of the video signal between individual screen points. Therefore this configuration can only be envisaged for small screens.
In this connection it is possible to calculate the delay introduced at the end of the column. The time constant of the end of the column is approximately t'=RC/2, if R is the total resistance of the column and C is total capacity. We obtain R=(r.multidot.L)/(d.multidot.w) with r=resistivity, L=length, d=thickness and w=width.
Moreover, we have C=Cmo+Cx+Ccl with Cmo being the column/optical mask capacity, Cx the row/column intersection capacity, Ccl the liquid crystal capacity (column/counterelectrode), EQU Cmo=(e.sub.1 .multidot.w.multidot.L)/d.sub.i, Cx=N.multidot.(e.sub.j .multidot.w.multidot.w)/d.sub.j, Ccl=(e.sub.k .multidot.w.multidot.L)/d.sub.k,
with e and d respectively being the dielectric constant and thickness of the insulators (i, j and k representing the insulator of the optical mask, an intersection and the liquid crystal).
It can easily be seen that Cmo/Ccl&gt;10, because dk=5 microns and d.sub.i =0.5 micron and e.sub.i differs only slightly from e.sub.k. Moreover, generally Ccl differs only slightly from Cx.
Thus, if without an optical mask the column has a capacity of 2 (in arbitrary units), it will be 12 with the optical mask (in unity measurements). Therefore, the corresponding time constant will be six times higher. It can therefore be concluded that the column limit length is six times smaller in this case. This limit length is that for which the column delay becomes incompatible with, the addressing time.
In the aforementioned document, it is possible to see in the drawings, that the material constituting the column and the pixel is conductive and transparent ITO. With an ITO of square resistance 10 Ohms, the limit length is approximately 25 cm without an optical mask below the columns. It will be less than 5 cm on placing an optical mask below the columns.